The present invention relates to a digital-to-analogue (D/A) converter and an analogue-to-digital (A/D) converter. More particularly, the present invention concerns a signal processing circuit such as pulse duration generating circuit or the like for determining integration time of an integration type D/A converter and A/D converter of low power consumption and improved linearity.
As typical integration type D/A converter and A/D converter employed heretofore in the digital audio-signal recording/reproducing apparatus, there can be mentioned those disclosed in Japanese Patent Application Laid-Open Nos. 99821/1982 and 197910/1982 (JP-A-5799821 and JP-A-57-197910). More specifically, Japanese Patent Application Laid-Open No. 99821/1982 discloses an integration-type 16-bit D/A converter in which currents of two constant current sources weighted in the ratio of 1 to 2.sup.8 are charged in a capacitor constituting a part of integrator for periods corresponding to data placed in an eight more significant bit (MSB) counter and an eight less significant bit (LSB) counter, respectively, to derive an analogue output signal. Assuming, for example, that the sampling period is 20 .mu.sec (sampling frequency =50 KHz), the time T taken for conversion is 10 .mu.sec and that the number N of bits is equal to eight, the clock frequency f required for the counter is given by ##EQU1## Thus, the D/A converter can be realized in the form of a monolithic IC. Further, by dividing the input data into three or more parts, the clock frequency required for the counters can be further decreased.
On the other hand, Japanese Patent Application Laid-Open No. 197910/1982 discloses an integration type 16-bit A/D converter in which two current sources of current values weighted in the ratio of 1 to 2.sup.7 are provided in correspondence with nine more significant bits and seven less significant bits, respectively, wherein an analogue value sampled at an integrator element is roughly discharged with the current weighted "2.sup.7 ", being followed by the discharge with the current weighted "1", while counting the time taken for the discharge, to thereby obtain 16-bit digital data. The clock frequency f required for the counter is about 50 MHz on the assumption that the sampling period is about 20 .mu.sec. With this arrangement, the A/D converter can be realized in a monolithic IC structure. By providing more than two weighted current sources and counters, respectively, the clock frequency required for the counter can be further decreased.
In conjunction with implementation of the D/A converter and A/D converter, bipolar process is suited for realizing the current source circuits and current switch circuits constituting parts of the converters in respect to attainable high accuracy, low noise and high speed. In that case, however, when implementation in the monolithic IC is prerequisite, the counters must be constituted by using logic elements such as ECL (emitter-coupled logic) or the like of large scale and high power consumption. In this conjunction, no consideration is paid to the power consumption in the hitherto known techniques.
Further, since the current value of the current source for the more significant bit data is 256 times (128 times in the case of the A/D converter) as large as that of the current source for the less significant bit data, there is produced error when the signal for controlling the periods of charge and discharge is deviated due to the switching jitter. In the case of the D/A converter, the permissible value of jitter is ##EQU2## on the assumption that the clock frequency is 25 MHz.
It is observed that the output linearity of the A/D and D/A converters implemented in IC undergoes degradation due to the jitter of the counter clock signal. FIG. 14 of the accompanying drawings illustrates graphically a relation between the clock jitter and S/N ratio. More specifically, this figure illustrates a modulation degree versus S/N characteristic of an integration type D/A converter in which the clock signal is frequency-modulated. As will be seen in the figure, a curve 33 of -6 dB/oct is obtained, which means that S/N ratio (and hence dynamic range) is degraded due to the clock jitter.